The formation of semiconductor devices involves the fabrication of isolation structures that provides isolation between individual semiconductor devices. Thus, in order to fabricate effective integrated circuits (ICs), isolation devices must first be formed in the silicon substrate. Ineffective isolation will cause leakage currents. Even a small amount of leakage in a device can induce significant power dissipation for the overall circuit in ultra large scale integrated circuits (ULSI). Several different isolation technologies have been proposed, including LOCOS (LOCal Oxidation of Silicon), shallow trench isolation (STI), LOCOS-based isolation such as poly-buffered LOCOS (PBL), and framed-mask PBL technologies.
The most widely used method for forming isolation regions is LOCOS. As device geometry has shrunk to the sub-half micron order, conventional LOCOS isolation cannot meet the requirements of ULSI fabrication. The major drawback of LOCOS is the "bird's beak" effect. In this effect, the oxidant laterally diffuses at the edges of the silicon nitride during the formation of the isolation. Oxide forms under the nitride edges and lifts the nitride edges. This lateral extension of the field oxide causes unacceptably large encroachment on the field oxide into the device active regions. Further, the planarity of the surface topography is inadequate for sub-micron lithography needs.
Trench isolation is used primarily for isolating devices in VLSI and ULSI, and hence it can be considered as a replacement for conventional LOCOS isolation. Further, shallow trench isolation is gaining popularity for quarter-micron technology. In the basic shallow trench isolation (STI) technology, shallow trenches are anisotropically etched into the silicon substrate. Next, a CVD oxide is deposited onto the substrate and is then planarized by CMP (Chemical Mechanical Polishing) or etching back.
Unfortunately, the planarization of shallow trench isolation relies on chemical mechanical polishing (CMP) which has proven an effective but challenging process. For example, one of the issues associated with CMP for STI is the dishing effect for wide trenches. :The dishing effect makes it difficult to obtain a planar surface. In addition, it also impacts the control of subsequent processes, such as lithography and ion implantation.
One prior art approach to this issue is the use of a dummy pattern. Although the use of this conventional method can improve the result of CMP planarization, it is a complicated task that involves the additional steps of lithography and etching. Further, the CMP also exhibits the characteristics of bad uniformity over the entire wafer, pattern-dependent polishing uniformity and instability of polishing rate.